The present invention relates to a ferroelectric memory.
The ferroelectric memory is a novel memory which has been recently gained attention due to several advantageous features such as non-volatile memory, high-speed operation, a large number of write/erase cycles, and low power consumption.
Hitherto, several types of ferroelectric memories are known. Of them, studies have been aggressively made on a ferroelectric memory constituted of 1T/1C type memory cells each consisting of a single transistor and a single capacitor.
FIG. 1 shows a 1T/1C type memory cell of the ferroelectric memory.
As is apparent from the figure, the memory cell bears a striking resemblance to a dynamic random access memory (DRAM). The memory cell differs from the DRAM in the following points. First, a cell capacitor is formed of a ferroelectric capacitor. Second, an end of the cell capacitor is not connected to a line supplying a fixed potential (ground potential GND, a half of a power source potential: VCC) but connected to a plate line such that a potential can be set independently in every memory cell.
In the ferroelectric memory, data program and data read operations are performed by use of hysteresis characteristics of the ferroelectric material constituting the ferroelectric capacitor.
FIG. 2 shows the hysteresis characteristics of the ferroelectric capacitor.
Data of the memory cell are recognized by the polarization direction of the ferroelectric capacitor. In FIG. 2, a voltage to be applied to the ferroelectric capacitor is defined as follows. If the potential of a bit line BL is higher than that of a plate line PL, the voltage is regarded as a "minus voltage". On the other hand, if the potential of the plate line PL is higher than that of the bit line BL, the voltage is regarded as a "plus voltage". Furthermore, a residual polarization point c corresponds to data "0" and a residual polarization point a corresponds to data "1".
When the data "0" is programmed (input) into a memory cell, a transfer gate is turned on, and then, a voltage (0V) is applied to the bit line BL and a plus potential (voltage) is applied to the plate line PL. Thereafter, when the potential to be applied to the plate line PL is changed to 0V, the polarization point moves from a point b to a point c, with the result that data "0" is programmed (input) into the memory cell.
Similarly, when data "1" is programmed into a memory cell, the transfer gate is turned on, and then, a plus potential is applied to the bit line BL and the voltage "0V" is applied to the plate line PL. Thereafter, when the potential to be applied to the bit line BL is changed to 0V, the polarization point moves from a point d to a point a, with the result that the data "1" is programmed (input) into the memory cell.
The data read operation is performed by detecting an amount of charge released from the ferroelectric capacitor to the bit line BL when a predetermined potential is applied to the plate line PL. For example, if the bit line BL is set in a floating state, and thereafter, the transfer gate is turned on to apply a plus potential to the plate line PL, charge (.DELTA.Q1 in amount) is released to the bit line BL when the data of the selected memory cell is "1". In contrast, when the data of the selected memory cell is "0", charge (.DELTA.Q0 in amount) is released to the bit line BL.
Thus, the data of the memory cell selected can be determined by detecting the difference in charge amount. As a result, accurate data can be read out of the memory chip.
As a method of determining the data, employed is a method of comparing the potential of the bit line BL connected to the memory cell selected with the potential of the bit line BL connected to a reference cell.
When the potential of the bit line BL is set at V1 by the supply of the charge .DELTA.Q1 and the potential of the bit line BL is set at V0 by the supply of the charge .DELTA.Q0, it is desirable that the potential of the bit line BL connected to a reference cell be set at (V0+V1)/2.
The reference cell is selected every time the access operation is repeated. Thus, if the reference cell is formed of a ferroelectric capacitor, polarization fatigue takes place in the ferroelectric capacitor every time the access operation is repeated. As a result, no charge is released from the reference cell.
On the other hand, in the case where the reference cell is formed of a paraelectric capacitor, a relative dielectric constant of the paraelectric capacitor is lower than that of the ferroelectric capacitor, so that the size of the reference cell inevitably increases. Therefore, this case is disadvantageous to high integration.
Up to now, no proposals have not been made for a circuit arrangement of a dummy plate driver useful for high integration of devices.